The standard D flip-flop frequency-delta-sigma modulator. | Download Scientific Diagram
FPGA sketch containing sampled-clock D flip-flop and sinc 2 decimator.... | Download Scientific Diagram
A 100-Mhz Bandwidth 80-dB Dynamic Range Continuous-Time Delta-Sigma Modulator with a 2.4-Ghz Clock Rate | Discover Nano
Electronics | Free Full-Text | 9.9 µW, 140 dB DR, and 93.27 dB SNDR, Double Sampling ΔΣ Modulator Using High Swing Inverter-Based Amplifier for Digital Hearing Aids
Power optimisation of single phase clocked feedback D flip-flop for CDMA
PDF] FPGA based sigma – Delta analogue to digital converter design | Semantic Scholar
VHDL Implementation of Sigma-Delta Analog To Digital Converter
Figure 3 from Comparative analysis of D flip-flops in terms of delay and its variability | Semantic Scholar